1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the partitioning of results containing multiple result data values within single instruction multiple data (SIMD) data processing systems.
2. Description of the Prior Art
It is known to provide data processing systems with SIMD capabilities. In such systems a register typically contains multiple independent data values to be manipulated. As an example, a 32-bit register may contain two independent 16-bit data values which are to be separately added to, multiplied with or otherwise combined with, for example, two other 16-bit data values stored within another 32-bit register. Such SIMD operations are common in the field of digital signal processing and have advantages including increased processing speed and reduced code density.
An example of known SIMD techniques are the MMX instructions of the Intel processors produced by Intel Corporation. In the MMX instructions are included instructions which multiply together two registers each containing four 16-bit data values. When a 16-bit data value is multiplied by another 16-bit data value, then the result is a 32-bit data value. Accordingly, when the four pairs of 16-bit data values specified in the MMX SIMD instruction are multiplied together, the result is four 32-bit result data values. In many circumstances it is desired to maintain the SIMD format and data size when such operations are performed. To this end, the MMX instructions include a type of instruction in which in the above circumstance the result generated is in the form of four 16-bit result data values being the 16 most significant bits of the respective 32-bit result with these 16-bit values being combined within a single 64-bit register, i.e. producing a SIMD-type result. As an alternative, it is also possible to have separate instructions which generate the four least significant 16-bits of the multiplication result as their output combined in a 64-bit register.